1. Field of the Invention
The present invention relates to a memory device which employs multilevel memory circuits (multilevel memory cells), and more particularly to a high-speed, multilevel DRAM (Dynamic Random Access Memory) structure which permits increased speed during memory operation and reduction of the bit area (an area necessary for storing one bit).
2. Description of the Related Art
Heretofore there have been proposed a variety of memory devices of the type that have m.n (where m.ltoreq.1 and n.ltoreq.1 m,n: integer) memory cells M.sub.11 to M.sub.1n, M.sub.21 to M.sub.2n . . . and M.sub.m1 to M.sub.mn, m bit lines (data lines) A.sub.1 to A.sub.m, m column select lines B.sub.1 to B.sub.m and n word lines C.sub.1 to C.sub.m and in which, in the state of one of the memory cells M.sub.1j to M.sub.mj (where j=1 to n) is selected by a word select signal from the word line C.sub.j, information is provided on the bit line A.sub.i using a column select signal from the column select line B.sub.i for storage in the memory cell M.sub.ij and the information is read out of the data line A.sub.i using a column select signal from the column select line B.sub.i.
In general, however, conventional memory devices are arranged so that binary information of one bit, which assumes a "1" or "0" in the binary representation, is stored in or read out of the memory cell M.sub.ij.
Because of this, the overall storage capacity of the memory device is limited specifically to m.times.n bits which is equal to the number of memory cells M.sub.1l to M.sub.1n, M.sub.21 to M.sub.2n, . . . and M.sub.ml to M.sub.mn. Accordingly, an increase in the overall storage capacity of the memory device will call for an increase in the number, m.times.n, of the memory cells, resulting in the memory device as a whole becoming bulky as.